cowos

Supply chain sources say that TSMC's wafer foundry prices are set to rise again, with adjustments to Wafer Out prices based on different processes starting from January 2027, with an increase of about 3% to 6%. The utilization rate of 8-inch factories exceeds 100%, and processes below 45 nanometers are fully loaded, with order visibility extending to 2030. The increase for advanced processes is higher, while mature and specialty processes are negotiated individually based on products, utilization rates, and customer conditions. TSMC has not responded to market rumors.Supply chain sources indicate that TSMC's 2-nanometer and 3-nanometer processes are in short supply, and the pressure on advanced packaging capacities such as CoWoS has not been alleviated. Customers find it difficult to switch suppliers immediately even in the face of price increases. The factory in Arizona, USA, reflects higher manufacturing costs, and the foundry quotes remain high. After the price adjustment, quotes from foundries such as Samsung Electronics, Intel, United Microelectronics Corporation, and World Advanced, as well as testing and packaging factories and IC design customers, may also be affected. United Microelectronics Corporation, Powerchip Semiconductor Manufacturing Corporation, and World Advanced have announced price increase strategies, which will continue until 2027.The supply chain states that this wave of AI demand has increased the need for PMIC, MCU, driver ICs, analog ICs, and sensors, in addition to GPUs, ASICs, and HBM. IC design companies point out that after the wafer price increase, product costs need to be reassessed, with higher-end GPUs and ASICs having relatively larger pass-through space. TSMC Chairman Wei Zhejia has stated that customers do not switch wafer foundry partners just because they are dissatisfied today. Supply chain sources say that orders transferred from Google, Apple, NVIDIA, and others mostly involve non-core chips or limited-scale orders, with no significant changes observed in the high-end process customers' chip placements.

As we enter the late third quarter of 2026, TSMC's 3nm and 2nm advanced process and CoWoS advanced packaging capacity continue to be in high demand. NVIDIA and Apple continue to dominate the resources for advanced processes and packaging; Amazon AWS's Annapurna has recently increased its AI self-developed chip production, securing more 3nm capacity. MediaTek, in addition to mobile chips, is also competing for 2/3nm process and CoWoS-S/L capacity with large orders related to Google TPU.There are reports that TSMC has recently readjusted its capacity allocation. After MediaTek secured a large order from Google TPU, the next-generation TPU v9 will simultaneously use TSMC's CoWoS-L and Intel's EMIB-T, which has slightly adjusted MediaTek's 3nm and 2nm capacity arrangements. Currently, TSMC's main customer for 3nm is NVIDIA, which is expected to surpass Apple to become the largest customer by 2025; the demand for 2nm is primarily from Apple and others. After AWS increased Annapurna's production, its 3nm and CoWoS configuration priority has improved.Starting in early 2026, TSMC will accelerate capacity expansion, with the 2nm monthly capacity of Hsinchu Baoshan Fab 20 and Kaohsiung Fab 22 reaching 50,000 wafers each by the end of October, totaling about 100,000 wafers; by the end of October, the monthly capacity for 3nm in Tainan Science Park is about 185,000 wafers. As of the end of September, the overall capacity utilization rate is about 96.2%, with 100% utilization for processes below 16/12nm down to 2nm. The shortage of CoWoS supply has driven advanced packaging orders to overflow, with the priority for orders going to ASE Group's Siliconware Precision Industries first, followed by Amkor, and Chipbond, among others. Chipbond's related testing and packaging capacity is fully loaded, with order visibility extending to 2028.

According to Taiwan's "Commercial Times" report on September 14, as the computing power of GPUs and ASICs continues to rise, traditional copper interconnects are gradually approaching the limits of power consumption and signal transmission. TSMC is accelerating its layout for co-packaged optics (CPO). The industry is optimistic that if CPO bandwidth continues to double every two years, it may form the "CPO Moore's Law" of the AI era. Industry analysis indicates that the upgrade of CPO bandwidth mainly has three paths: including increasing single-channel speed from 200G to over 400G, expanding the number of optical channels from 16 to 32, 64 or more, and introducing wavelength division multiplexing (WDM). By 2040, the theoretical value could reach about 128 times the current level, with long-term potential for development towards hundreds of T based on the current level of about 3.2T.TSMC's role in optical interconnects has extended from wafer foundry to system integration, gradually integrating computing, HBM memory, and high-speed I/O from 3DFabric, CoWoS, SoIC to silicon photonics and CPO. When high-speed electrical signals exceed 200G, signal attenuation increases after passing through longer copper paths such as ABF substrates, PCBs, and connectors, leading the industry to develop shorter copper paths and longer optical paths. In terms of packaging architecture, the optical engine is currently laid out on the substrate, and the next step is expected to place CPO in the intermediary layer, with future possibilities of using SoIC technology to achieve 3D vertical integration of photonic integrated circuits (PIC) and ASICs. Industry players indicate that CPO still needs to overcome challenges in packaging, optical coupling, and testing before mass production can be achieved.

According to the Economic Daily, TSMC's advanced packaging CoWoS capacity is in short supply, and it has been reported that some backend orders have overflowed to Intel's factory in Malaysia, where Intel is assisting with packaging using part of its capacity to serve common major customers, breaking the past ecosystem competition norms. TSMC Chairman Wei Zhejia previously stated at a conference call that TSMC focuses on advanced packaging in the frontend and welcomes "more manufacturers to supply capacity" for the shortage in the backend, providing flexible alternatives for common customers.The report points out that the bottleneck in advanced packaging capacity mainly lies in the backend ramp-up speed being lower than that of the frontend process, and the widening gap in CoWoS capacity has forced orders to overflow. SemiAnalysis Chipbook data shows that approximately $1.3 billion worth of HBM has been shipped to Malaysia, and industry analysis indicates that Intel's local factory should already have the capability for large-scale HBM integration. Intel CEO Pat Gelsinger stated that the EMIB-T technology is ensuring reliable yield, and in the context of insufficient CoWoS capacity, "Intel is in a unique position to provide support." Companies with overlapping supply chains such as Unimicron, ASE Technology Holding, and Jiadeng are expected to benefit simultaneously, with Unimicron's stock price rising over 7% on that day. Intel's EMIB-T related applications are targeted for mass production by 2027.