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first_img Samsung Electronics executive: It is expected that HBM will account for nearly 30% of DRAM wafer production capacity next year

According to a report by the Financial Associated Press citing local media on September 29, Samsung Electronics Executive Vice President Kim Taewoo stated that HBM is expected to account for nearly 30% of the total wafer capacity of DRAM manufacturers next year, up from the current ratio of about 20%. He mentioned that HBM competes with traditional DRAM for the same batch of wafer capacity, and increasing HBM output may squeeze the supply of traditional DRAM.TrendForce previously predicted that by the end of 2027, the HBM wafer input from the three major global HBM suppliers will account for about 30% of the total DRAM wafer input, but in terms of storage capacity, it will only contribute about 13% of the total DRAM supply. Additionally, according to media reports on September 20, Samsung began mass production and shipment of HBM4 in February this year and provided 12-layer HBM4E samples to customers including NVIDIA in May; the industry expects Samsung's monthly wafer input for HBM to increase from about 180,000 wafers this year to about 250,000 wafers next year.On the same day, TrendForce stated that the demand for AI servers continues, and HBM and general DRAM will still share limited advanced process capacity. The storage supply will remain tight in 2027, and the price expectations for HBM in 2027 have been raised, with an expected year-on-year increase of 121% in the mixed average selling price. Due to limited supply and rising system costs, 8-layer HBM is expected to become a priority evaluation option for several manufacturers in 2027, with its price per Gb expected to be about 10% to 20% higher than that of 12-layer products.

first_img Samsung Electronics accelerates the construction of the first mass production line in Pyeongtaek P5, with the equipment introduction target moved up to the second quarter of next year

According to a report by ZDNet Korea on September 28, Samsung Electronics is accelerating the construction of the first mass production line (Ph1) at the Pyeongtaek Fifth Campus (P5) and is discussing with major equipment manufacturers to move the target for Ph1 equipment installation from the originally planned third quarter of next year to the second quarter of next year. P5 is the next-generation semiconductor production base aimed to be operational by 2028, and the construction of the Ph1 cleanroom began in the third quarter of this year.Samsung Electronics had previously advanced the completion of the P5 Ph1 cleanroom, originally scheduled for early next year, by about six months, so the equipment installation is expected around the third quarter of next year. Industry insiders say that the start time for equipment installation is planned to be moved up from July to August next year to around May to June next year; others have indicated that Samsung has even proposed to deliver equipment in the first quarter of next year for temporary storage at other locations, showing a strong willingness to invest early.Discussions on the investment for the second phase of P5 (Ph2) are also progressing. Currently, Ph1 is more likely to be built as a DRAM and HBM production line, while Ph2 is more likely to be built as an advanced NAND production line, including the tenth generation (V10). Equipment industry insiders say that formal purchase orders have not yet been placed, but Samsung has discussed building Ph2 as a NAND production line with partners, and due to the long equipment delivery cycle, they are requesting to prepare relevant components in advance. Reports indicate that large global tech companies are increasing orders for high-performance DRAM and NAND for AI infrastructure, while storage companies like Samsung have limited production capacity. Samsung stated during the second quarter earnings call in July that unmet demand this year will extend into next year, and the supply shortage next year will be more severe than this year, with shortages expected to continue until 2028.

first_img Samsung Electronics adjusts the next-generation DRAM roadmap, naming B1b as D0a

According to a report by ZDNet Korea, Samsung Electronics is adjusting its next-generation DRAM strategy by incorporating the previously project-based B1b into its official roadmap, naming it the first DRAM D0a below 10 nanometers. Previously, D0a referred to vertical transistor DRAM, and this product is now classified separately as D0a-V. This renaming aims to accelerate the introduction of advanced packaging in general DRAM.B1b will manufacture storage cells and peripheral driver circuits on different wafers before bonding them together, using wafer-to-wafer hybrid bonding and directly connecting through copper interconnects. The currently commercialized DRAM is 1c, which is the 6th generation 10 nanometer level, with a line width of about 11 to 12 nanometers; the next generation 1d is the 7th generation 10 nanometer level, with a line width of about 10 to 11 nanometers, considered effectively the last 10 nanometer level product, with the related line width being a marketing term rather than an actual physical size. Vertical transistors can arrange transistors within the cell vertically, reducing the cell area from 6F² to 4F², but they need to address high aspect ratio etching and leakage current, making development more challenging. Wafer-to-wafer hybrid bonding has already been mass-produced in CMOS image sensors and high-stacking NAND.Samsung Electronics is evaluating the use of B1b for the 8th generation high bandwidth memory HBM5. HBM5 is expected to be mass-produced around 2029, aiming to increase operating speed by more than 50% compared to HBM4E. Industry estimates suggest that D0a DRAM based on B1b will be commercially available in about two years, with specific mass production investment schedules likely to be determined by mid-next year.

first_img Samsung Electronics plans to expand production of 4-nanometer to meet HBM4 demand

According to Money Today on September 21, Samsung Electronics is advancing the expansion of advanced process capacity in wafer foundry due to the growth of the HBM market. To meet the rising demand for HBM4 base chips, it is evaluating the expansion of its 4-nanometer process. Samsung's HBM4 consists of 10-nanometer 6th generation (1c) DRAM core chips and 4-nanometer logic base chips, with the base chips responsible for high-speed data exchange with AI accelerators such as GPUs.Unlike SK Hynix, which uses TSMC's 12-nanometer process for HBM4 base chips, Samsung employs its own 4-nanometer process. This production line is operating at full capacity and has taken on orders from companies like Nvidia and Groq for 3 LPU, and the company has recently raised its prices for new 4-nanometer orders and HBM4 base chips. Samsung expects HBM4 revenue in the third quarter to increase more than threefold quarter-on-quarter, with HBM4 accounting for significantly more than 60% of HBM revenue in the second half of the year. The additional expansion at P4 in Pyeongtaek will mostly be used for 1c DRAM for HBM, with more than half of the wafer foundry's 4-nanometer capacity allocated to HBM4 base chips.HBM4E also uses 4-nanometer base chips, and Samsung provided samples to customers in May. The company is also evaluating the construction of a new 2-nanometer production line for HBM5, aiming for a GAA structure 2-nanometer process and increasing TSV density to improve operating speed by more than 50% compared to HBM4E. Samsung started the first generation of 2-nanometer mass production in the second half of last year and is advancing the second generation of products in the second half of this year. Citigroup expects global HBM bit demand to reach 75.2 billion Gb next year, a year-on-year increase of 62%, with supply around 59.4 billion Gb and a gap of about 21%.
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